1. MAX® 10 High-Speed LVDS I/O Overview
2. MAX® 10 High-Speed LVDS Architecture and Features
3. MAX® 10 LVDS Transmitter Design
4. MAX® 10 LVDS Receiver Design
5. MAX® 10 LVDS Transmitter and Receiver Design
6. MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for the MAX® 10 High-Speed LVDS I/O User Guide
3.3.2. Sub-LVDS Transmitter External Termination
The Sub-LVDS transmitter requires a three-resistor external termination scheme.
Figure 10. External Termination for Sub-LVDS Transmitter