Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 2.5G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels.
- Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
- Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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