AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

PHY Interface Signals

Table 7.   PHY Interface Signals
Signal Direction Width Description
rx_serial_data[] In 2 RX serial input data
tx_serial_data[] Out 2 TX serial output data
led_link[] Out 2 Asserted when the link synchronization for 1GbE or 2.5GbE is successful.
led_char_err[] Out 2 Asserted when a 10-bit character error is detected in the RX data.
led_disp_err[] Out 2 Asserted when a 10-bit running disparity error is detected in the RX data.
led_an[]   2 Asserted when auto-negotiation is completed.
channel_tx_ready[] Out 2 The signal bit is asserted when the TX datapath of the channel is ready for data transmission.
channel_rx_ready[] Out 2 The signal bit is asserted when the RX datapath of the channel is ready for data transmission.
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