AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 11.   Register Map
Byte Offset Block
0x00_0000 Transceiver Reconfiguration
0x00_4000 Reserved
Channel 0
0x01_0000 MAC
0x01_8000 PHY
0x01_A000 Native PHY Reconfiguration
Channel 1
0x02_0000 MAC
0x02_8000 PHY
0x02_A000 Native PHY Reconfiguration
Traffic Controller
0x10_0000 Traffic Controller
Level Two Title