AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Transceiver Reconfiguration

Table 12.  Transceiver Reconfiguration Register Map
Word Offset Name Bits Description Access HW Reset
0x00 logical_channel_number [9:0] The logical number of the reconfiguration block. RW 0x000
[31:10] Reserved — —
0x01 control [1:0] Specify the new operating speed:
  • 00: 1 Gbps
  • 01: 2.5 Gbps
  • 10: Reserved
  • 11: 10 Gbps
 RW 0x00
[15:2] Reserved — 0x000
[16]

Writing 1 to this bit when it is 0 starts the reconfiguration process. The bit clears when the process is completed.

RWC 0x0
[31:17] Reserved — 0x000000
0x02 status [0] When set to 1, indicates the reconfiguration process is in progress. RO 0x0
[31:1] Reserved — —
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