AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Packet Classifier Interface Signals

Table 9.   Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_in_valid[] In 2 Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_in_fingerprint[][] In [2][TSTAMP_FP_WIDTH] Use this bus to specify the fingerprint that validates the timestamp for the incoming packet.
clock_operation_mode_mode[][] In [2][2] Use this signal to specify the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] In 2 Use this signal to specify whether or not a packet contains CRC.
  • 0: Packet contains CRC
  • 1: Packet does not contain CRC
tx_ingress_timestamp_valid[] In 2 Indicates whether or not the residence time can be updated.
  • 0: Prevents update for residence time
  • 1: Allows update for residence time based on decoded results

When this signal is deasserted, the tx_etstamp_ins_ctrl_out_residence_ti me_update signal also gets deasserted.

tx_ingress_timestamp_96b_data[][] In [2][96] 96-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_64b_data[][] In [2][64] 64-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_format[] In 2 The format of the timestamp for calculating the residence time.
  • 0: 96 bits
  • 1: 64 bits
This signal must be aligned to the start of an incoming packet.
Level Two Title