AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Hardware Testing

Follow these steps to compile and test the design in the supported Altera development kit:
  1. Launch the Quartus Prime software and compile the design (Processing > Start Compilation).

    The timing contraints for the design example and the design components are automatically loaded during compilation.

  2. Connect the development board to the host computer.
  3. Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).
  4. Launch the Clock Control tool, which is part of the development kit, and set new frequencies for the design example.
    Note: The chapter that describes the design example states the frequencies to set.
  5. Reset the system by pressing the PB0 push button.
  6. In the Quartus Prime software, launch the system console (Tools > System Debugging Tools > System Console).
  7. Change the working directory to <Example Design>\hwtesting\system_console.
  8. Initialize the design command list by running this command, source main.tcl.
  9. You can now run any of the predefined hardware tests from the System Console. Observe the test results displayed.
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