AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Avalon-MM Interface Signals

Use the prefixes to identify the Avalon-MM interface signals for the following design components:
  • MAC—csr_mac_*
  • PHY—csr_phy_*
  • Transceiver Reconfiguration—csr_rcfg_*
  • Arria® V Native PHY Reconfiguration—csr_native _phy_rcfg_*
  • Master TOD—csr_master_tod_*
Table 5.   Avalon MM Interface Signals
Signal Direction Width Description
csr_mac_write[] In 2 Assert the signal to request a write. For the MAC, PHY, and Master TOD, assert bit 0 to request a write to channel 0; bit 1 for channel 1.
csr_phy_write[] 2
csr_rcfg_write 1
csr_native _phy_rcfg_write 1
csr_master_tod_write[] 2
csr_mac_read[] In 2 Assert the signal bit to request a read. For the MAC, PHY, and Master TOD, assert bit 0 to request a read from channel 0; bit 1 for channel 1.
csr_phy_read[] 2
csr_rcfg_read 1
csr_native _phy_rcfg_read 1
csr_master_tod_read[] 2
csr_mac_address[][] In [2][10] Use this bus to specify the register address you want to read from or write to.
csr_phy_address[][] [2][5]
csr_rcfg_address[] 2
csr_native _phy_rcfg_address[] 10
csr_master_tod_address[][] [2][4]
csr_mac_writedata[][] In [2][32] Data to be written to the specified register.
csr_phy_writedata[][] [2][32]
csr_rcfg_writedata[] 32
csr_native _phy_rcfg_writedata[] 32
csr_master_tod_writedata[][] [2][32]
csr_mac_readdata[][] Out [2][32] Data read from the specified register.
csr_phy_readdata[][] [2][32]
csr_rcfg_readdata[] 32
csr_native _phy_rcfg_readdata[] 32
csr_master_tod_readdata[][] [2][32]
csr_mac_waitrequest[] Out 2 When asserted, this respective signal bit indicates that the channel is busy and not ready to accept any read or write requests.
csr_phy_waitrequest[] 2
csr_native _phy_rcfg_waitrequest 2
csr_master_tod_waitrequest[] 2
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