AN 757: 1G/2.5G Ethernet Design Examples

ID 683753
Date 11/12/2018
Public
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Reset Scheme

The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.

Figure 3. Reset Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature
Figure 4. Reset Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature