Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

5.2. GPIO Lite Intel® FPGA IP Interface Signals

Depending on parameter settings you specify, different interface signals are available for the GPIO Lite IP core.
Table 29.  Pad Interface SignalsThe pad interface connects the GPIO Lite IP core to the pads.
Signal Name Direction Description
pad_in Input

Input pad port if you use the input path.

pad_in_b Input

Input negative pad port if you use the input path and enable the true or pseudo differential buffers.

pad_out Output

Output pad port if you use the output path.

pad_out_b Output

Output negative pad port if you use the output path and enable the true of pseudo differential buffers.

pad_io Bidirectional

Bidirectional pad port if you use bidirectional paths.

pad_io_b Bidirectional

Bidirectional negative pad port if you use bidirectional paths and enable true or pseudo differential buffers.

Table 30.  Data Interface SignalsThe data interface is an input or output interface from the GPIO Lite IP core to the FPGA core.
Signal Name Direction Description
din Input

Data received from the input pin.

Signal width for each input pin:

  • DDR mode—2
  • Other modes—1
dout Output

Data to send out through the output pin.

Signal width for each output pin:

  • DDR mode—2
  • Other modes—1
oe Input

Control signal that enables the output buffer. This signal is active HIGH.

nsleep Input

Control signal that enables the input buffer. This signal is active LOW.

This signal is available for the 10M16, 10M25, 10M40, and 10M50 devices.

Table 31.   Clock Interface SignalsThe clock interface is an input clock interface. It consists of different signals, depending on the configuration. The GPIO Lite IP core can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.
Signal Name Direction Description
inclock Input

Input clock that clocks the registers in the input path.

inclocken Input

Control signal that controls when data is clocked in. This signal is active HIGH.

outclock Input

Input clock that clocks the registers in the output path.

ouctlocken Input

Control signal that controls when data is clocked out. This signal is active HIGH.

Table 32.  Reset Interface SignalsThe reset interface connects the GPIO Lite IP core to the DDIOs.
Signal Name Direction Description
aclr Input

Control signal for asynchronous clear that sets the register output state to 0. This signal is active HIGH.

aset Input

Control signal for asynchronous preset that sets the register output state to 1. This signal is active HIGH.

sclr Input

Control signal for synchronous clear that sets the register output to 0. This signal is active HIGH.
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