1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
184.108.40.206. Programmable Open Drain 220.127.116.11. Programmable Bus Hold 18.104.22.168. Programmable Pull-Up Resistor 22.214.171.124. Programmable Current Strength 126.96.36.199. Programmable Output Slew Rate Control 188.8.131.52. Programmable IOE Delay 184.108.40.206. PCI Clamp Diode 220.127.116.11. Programmable Pre-Emphasis 18.104.22.168. Programmable Differential Output Voltage 22.214.171.124. Programmable Emulated Differential Output 126.96.36.199. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
To minimize the impact of simultaneous switching noise (SSN) on the I/O pins, ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines in the following table.
|I/O Standard of Surrounding Pins||Locations Relative to 1.0 V Pin||Total Lm of Surrounding Pins|
|1.0 V||Within the same bank||The total Lm of the surrounding pins in the bank must not exceed 7.41 nH.|
|In an adjacent bank||The total Lm of the surrounding pins in the adjacent bank must not exceed 7.41 nH.|
|Within the same bank and in an adjacent bank||The sum of the total Lm of the surrounding pins in both banks must not exceed 7.41 nH.|
|Other than 1.0 V||In an adjacent bank||The total Lm of the surrounding pins in the adjacent bank must not exceed 1 nH.|
Example scenarios where the 1.0 V pin is in bank 3 and surrounding pins are in banks 3 and 4:
- Bank 3 and 4 are both 1.0 V—total Lm of all surrounding pins in both banks must not exceed 7.41 nH.
- Bank 3 is 1.0 V but bank 4 is 2.5 V—total Lm of surrounding pins in bank 3 must not exceed 7.41 nH and total Lm in bank 4 must not exceed 1 nH.
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