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1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
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2.3.2.4. Programmable Current Strength
You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.
I/O Standard | IOH / IOL Current Strength Setting (mA) (Default setting in bold) |
---|---|
3.3 V LVCMOS | 2 |
3.3 V LVTTL | 8, 4 |
3.0 V LVTTL/3.0 V LVCMOS | 16, 12, 8, 4 |
2.5 V LVTTL/2.5 V LVCMOS | 16, 12, 8, 4 |
1.8 V LVTTL/1.8 V LVCMOS | 16, 12, 10, 8, 6, 4, 2 |
1.5 V LVCMOS | 16, 12, 10, 8, 6, 4, 2 |
1.2 V LVCMOS | 12, 10, 8, 6, 4, 2 |
SSTL-2 Class I | 12, 8 |
SSTL-2 Class II | 16 |
SSTL-18 Class I | 12, 10, 8 |
SSTL-18 Class II | 16, 12 |
SSTL-15 Class I | 12, 10, 8 |
SSTL-15 Class II | 16 |
1.8 V HSTL Class I | 12, 10, 8 |
1.8 V HSTL Class II | 16 |
1.5 V HSTL Class I | 12, 10, 8 |
1.5 V HSTL Class II | 16 |
1.2 V HSTL Class I | 12, 10, 8 |
1.2 V HSTL Class II | 14 |
BLVDS | 16, 12, 8 |
SLVS | 16, 12, 8 |
Sub-LVDS | 12, 8, 4 |
Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.
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