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1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
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2.3.2.5. Programmable Output Slew Rate Control
You have the option of three settings for programmable slew rate control—0, 1, and 2 with 2 as the default setting. Setting 0 is the slow slew rate and 2 is the fast slew rate.
- Fast slew rate—provides high-speed transitions for high-performance systems.
- Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.
I/O Standard | IOH / IOL Current Strength Supporting Slew Rate Control |
---|---|
3.0 V LVTTL/3.0 V LVCMOS | 16, 12, 8 |
2.5 V LVTTL/2.5 V LVCMOS | 16, 12, 8 |
1.8 V LVTTL/1.8 V LVCMOS | 16, 12, 8 |
1.5 V LVCMOS | 16, 12, 10, 8 |
1.2 V LVCMOS | 12, 10, 8 |
SSTL-2 Class I | 12, 8 |
SSTL-2 Class II | 16 |
SSTL-18 Class I | 12, 10, 8 |
SSTL-18 Class II | 16, 12 |
SSTL-15 Class I | 12, 10, 8 |
SSTL-15 Class II | 16 |
1.8 V HSTL Class I | 12, 10, 8 |
1.8 V HSTL Class II | 16 |
1.5 V HSTL Class I | 12, 10, 8 |
1.5 V HSTL Class II | 16 |
1.2 V HSTL Class I | 12, 10, 8 |
1.2 V HSTL Class II | 14 |
You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew rate control. The slew rate control affects both the rising and falling edges.
Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.
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