Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 10/31/2022
Public
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4.1.1.2. DDR Output Path with Output Enable

Figure 17. Simplified View of GPIO Lite IP Core DDR Output Path with Output Enable


  • RegCo samples the data from IO_DATAOUT0 at the positive clock edge.
  • RegDo samples the data from IO_DATAOUT1 when outclock value is 0.
  • Output DDR samples the data from RegCo at the positive clock edge, and from RegDo at the negative clock edge.
Figure 18.  GPIO Lite IP Core Output Path Timing Diagram


  • The IP core feeds the first bit, D0, through IO_DATAOUT1 to RegDo. The IP core clocks out this bit at the RegDo QB port on a negative clock edge. At the next positive clock edge, the IP core produces the same bit at the multiplexer output.
  • The IP core feeds the second bit, D1, through IO_DATAOUT0 to RegCo. The IP core clocks out this bit at the RegCo Q port on a positive clock edge. At the next negative clock edge, the IP core produces the same bit at the multiplexer output.