3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
The Intel® Quartus® Prime software uses physics-based rules to define the number of I/Os allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance.
The physics-based rules are available for the following devices starting from these Intel® Quartus® Prime software versions:
- From Intel® Quartus® Prime version 14.1— Intel® MAX® 10 10M04, 10M08, 10M40, and 10M50 devices.
- From Intel® Quartus® Prime version 15.0.1— Intel® MAX® 10 10M02, 10M16, and 10M25 devices.
Geometry-Based Rules for Design Estimation
Intel highly recommends that you use the following geometry-based rules to ensure ADC performance. These guidelines help you to estimate the resources available and prevent additional critical warning from versions of the Intel® Quartus® Prime software that implements the physics-based rules.
|All||Disable all JTAG operation during ADC sampling. The ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation.|
Note: The GPIO pins in bank 8 are constrained by physics-based rules. The Intel® Quartus® Prime software issues a critical warning if the I/O settings violate any of the I/O physics-based rule. Table 20 only provides an example for your reference.
Note: The GPIO pins in banks 3, 5, and 7 are constrained by physics-based rules. The Intel® Quartus® Prime software issues a critical warning if the I/O settings violate any of the I/O physics-based rule. Table 21 only provides an example for your reference.
|I/O Standards||TX||RX||Total||Availability (%)|
|I/O Standards||Bank 3||Bank 5||Bank 7||Device I/O Availability (%)|
|TX||RX||Availability (%)||TX||RX||Availability (%)||TX||RX||Availability (%)|
|I/O Standard Group||I/O Standards Name and Drive Strength|
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