3.8. Guidelines: External Memory Interface I/O Restrictions
Two GPIOs Adjacent to DQ Pin Is Disabled
This limitation is applicable to Intel® MAX® 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use DDR3 and LPDDR2 SDRAM memory standards.
|Device Package||Memory Interface Width (DDR3 and LPPDR2 only)|
|F484||x8, x16, x24|
|F672||x8, x16, x24|
Total I/O Utilization in Bank Must Be 75 Percent or Less in Some Devices
If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use a maximum of 75 percent of the total number of I/O pins available in a bank. This restriction differs from device to device. In some devices packages you can use all 100 percent of the I/Os. The Intel® Quartus® Prime software will output an error message if the I/O usage per bank of that device is affected by this rule.
If you use DDR2 memory interface standards, you can assign 25 percent of the I/O pins as input pins only.
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