Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 10/31/2022
Document Table of Contents Programmable Bus Hold

Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.

The bus-hold circuitry holds the signal on an I/O pin at its last-driven state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

User I/O pins can be in either the default weak pull-up state or tri-state during configuration. With the bus-hold feature, if you do not drive the I/O pin externally when it enters user mode from configuration mode:
  • The I/O pin state is weak pull-up during configuration—the I/O pin retains the high value when the device enters user mode.
  • The I/O pin is tri-stated during configuration—the I/O pin value can be high or low when the device enters user mode.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.