Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

ID 683748
Date 12/04/2023

6.1. Performing Intel Agilex® 7 Boundary-Scan Testing

You can issue BYPASS, IDCODE, and SAMPLE JTAG instructions before, after, or during configuration without having to interrupt configuration.

To interrupt configuration in order to perform BST, you can either hold nCONFIG low or issue the following sequence through JTAG: an IR scan updating with 0x201 (COMMAND) followed by two 34 bit DR scans updating with 34’h3_0000_0000 then 35’h1_0000_0005. Once configuration is interrupted, you can issue other JTAG instructions to perform BST.

If you design a board for JTAG configuration using Intel Agilex® 7 devices, consider the connections for the dedicated configuration pins.

Dummy Bits

Dummy bits exist in the boundary-scan register during boundary-scan operations in Intel Agilex® 7 devices. However, these dummy bits do not have any impact on the pins. The dummy bits appear on the TDO immediately before the corresponding boundary-scan register segment and have an unknown value X, which can be either a 0 or 1.


For SoC FPGAs, you can only see the FPGA TAP controller in the JTAG chain upon device power up. The TAP controller for the HPS component only appears in the JTAG chain once the device is configured with a programming file or design that contains the HPS component. You must include the information about the HPS component when you generate the test patterns for the boundary-scan test. Download the boundary-scan description language (BSDL) file for the SoC FPGA from the Intel Agilex® 7 Device BSDL Files page.

F-Tile Devices

For F-Tile devices, if FHT support in F-Tile is disabled, the boundary-scan cell for the FHT channel is bypassed. Hence, the total boundary-scan length is reduced.

For F-Tile devices, if the F-Tile is powered down, the boundary-scan cell for the F-Tile is bypassed. Hence, the total boundary-scan length is reduced.