Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

ID 683748
Date 12/04/2023
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5.2. Disabling BST Circuitry

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 8.  Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Intel Agilex® 7 Devices
JTAG Pins4 Connection for Disabling
TMS VCCIO_SDM
TCK GND
TDI VCCIO_SDM
TDO Leave open
4 The JTAG pins are dedicated. Software option is not available to disable JTAG in Intel Agilex® 7 devices.