Visible to Intel only — GUID: vue1557391056493
Ixiasoft
1. Agilex® 7 JTAG BST Overview
2. Agilex® 7 JTAG BST Architecture
3. Agilex® 7 BST Operation Control
4. Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Agilex® 7 BST Circuitry
6. Agilex® 7 BST Guidelines
7. Document Revision History for the Agilex® 7 JTAG Boundary-Scan Testing User Guide
Visible to Intel only — GUID: vue1557391056493
Ixiasoft
2.1. JTAG Circuitry Functional Model
The JTAG BST circuitry requires the following registers:
- Instruction register—determines which action to perform and which data register to access.
- Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and TDO pins.
- Boundary-scan register—shift register composed of all the BSCs of the device.
Figure 1. JTAG Circuitry Functional Model
- Test access port (TAP) controller—controls the JTAG BST.
- TMS and TCK pins—operate the TAP controller.
- TDI and TDO pins—provide the serial path for the data and instruction registers.
Note: The TRST pin is not available in Agilex® 7 devices.