Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

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ID 683748
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 JTAG BST Overview 2. Intel Agilex® 7 JTAG BST Architecture 3. Intel Agilex® 7 BST Operation Control 4. Intel Agilex® 7 I/O Voltage for JTAG Operation 5. Enabling and Disabling Intel Agilex® 7 BST Circuitry 6. Intel Agilex® 7 BST Guidelines 7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide
2. Intel Agilex® 7 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel Agilex® 7 Device I/O Pin
3. Intel Agilex® 7 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Intel Agilex® 7 BST Guidelines x
6.1. Performing Intel Agilex® 7 Boundary-Scan Testing 6.2. Intel Agilex® 7 IEEE Std. 1149.1 BST Guidelines
1. Intel Agilex® 7 JTAG BST Overview
2. Intel Agilex® 7 JTAG BST Architecture
3. Intel Agilex® 7 BST Operation Control
4. Intel Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry
6. Intel Agilex® 7 BST Guidelines
7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

2.3.1. Boundary-Scan Cells of Intel Agilex® 7 Device I/O Pin

The Intel Agilex® 7 device 3-bit BSC consists of the following registers:

  • Capture registers—connect to internal device data through the OUTJ, OEJ, and PIN_IN signals.
  • Update registers—connect to external data through the PIN_OUT and PIN_OE signals.

The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (SHIFT, CLOCK, and UPDATE) internally. A decode of the instruction register generates the MODE signal.

The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.

Figure 3. User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Intel Agilex® 7 Devices


Note: TDI, TDO, TMS, TCK, TRST, VCC, GND, VREF, VSIGP, VSIGN, TEMPDIODE, and RREF pins do not have BSCs.
Table 2.   Boundary-Scan Cell Descriptions for Intel Agilex® 7 DevicesThis table lists the capture and update register capabilities of all BSCs within Intel Agilex® 7 devices.
Pin Type Captures Drives Comments
Output Capture Register OE Capture Register Input Capture Register Output Update Register OE Update Register Input Update Register
User I/O pins OUTJ OEJ PIN_IN PIN_OUT PIN_OE INJ —
Dedicated input 0 1 PIN_IN N.C. N.C. N.C. PIN_IN drives to the core logic
Dedicated bidirectional 1 0 OEJ PIN_IN N.C. N.C. N.C. PIN_IN drives to the core logic
Dedicated output 2 OUTJ 0 0 N.C. N.C. N.C. OUTJ drives to the output buffer
1 This includes the NCONFIG, MSEL0, MSEL1, and MSEL2 pins.
2 This includes the CONF_DONE and NSTATUS pins.
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