Agilex® 7 JTAG Boundary-Scan Testing User Guide

ID 683748
Date 11/04/2024
Public

4. Agilex® 7 I/O Voltage for JTAG Operation

The Agilex® 7 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 modes uses four required JTAG pins—TDI, TDO, TMS, and TCK.

The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have internal weak pull-up resistors. The VCCIO_SDM supply powers the TDI, TDO, TMS, and TCK pins.

The JTAG pins support 1.8 V LVCMOS I/O standard .

Note: For any voltages higher than 1.8 V, use a level shifter. Set the output voltage of the JTAG pins level shifter the same as the VCCIO_SDM supply.
Table 7.  TDO Output Buffer
TDO Output Buffer Condition Voltage (V)
VCCIO 3.3, 3.0, 1,8, 1.5