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2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. IP Catalog and Parameter Editor
2.3. Specifying the IP Core Parameters and Options
2.4. Simulating Intel® FPGA IP Cores
2.5. Simulating the Turbo IP with the RTL Simulator
2.6. Simulating the Turbo IP with the C-Model
2.7. Simulating the Turbo IP with MATLAB
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4. Turbo Intel® FPGA IP Functional Description
This topic describes the IP core’s architecture, interfaces, and signals.
You can parameterize the Turbo IP core as an encoder or a decoder.