Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP Core User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Core Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.6. Simulating the Turbo IP with the C-Model x
2.6.1. Encoder Simulation 2.6.2. Decoder Simulation
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
4.3. x
Signals in Platform Designer (Standard) Systems 4.3.1. Packet Format Errors
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP Core User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.3.

Signal names beginning with sink_* are the input interface to the Turbo IP. Signal names beginning with source_* are the output interface from the Turbo IP (excluding sink_ready and source_ready signals). Both interfaces comply with the Avalon Streaming specification with READY_LATENCY = 0.
Table 15.  Turbo Encoder Signals
Signal Direction Description
clk Input Clock signal that clocks all internal registers.
reset_n Input Active low reset signal. The IP core must always be reset before receiving data. If the megafunction is not reset, the Turbo encoder may produce unexpected results because of feedback signals.
sink_blk_size Input Specifies the incoming block size. This needs to be held throughout the whole incoming block, from sop to eop.
sink_data Input Input data.
sink_eop Input Indicates the end of an incoming packet.
sink_sop Input Indicates the start of an incoming packet.
sink_valid Input Asserted when data atsink_data is valid. When you deassert sink_valid, the IP core stops processing until you reassert sink_valid.
source_ready Input Asserted by the downstream module if it cannot accept data.
sink_error Input Error signal indicating Avalon-ST protocol violations on input side.
sink_ready Output Indicates when the IP core can accept data.
source_blk_size Output Specifies the outgoing block size, which is equal to K / N enc + ceil (4 / N enc).

Valid at source_sop.

source_data_s Output Output data.
source_eop Output Indicates the end of an outgoing packet.
source_error Output

Error signal indicating Avalon-ST protocol violations on source side:

  • 00: No error
  • 01: Missing start of packet
  • 10: Missing end of packet
  • 11: Unexpected end of packet

Other types of errors may also be marked as 11.

source_sop Output Indicates the start of an outgoing packet.
source_valid Output Asserted by the IP core when valid data is available to output.
Table 16.  Turbo Decoder Signals
Signal Direction Description
clk Input Clock signal that clocks all internal registers.
reset_n Input Active low reset signal. You must always reset the IP core before it receives data. If not reset, the Turbo decoder may produce unexpected results because of feedback signals.
CRC_pass Output

Indicates whether CRC was successful:

  • 0: Fail
  • 1: Pass
Note: This signal is present only in LTE mode.
CRC_type Output

Indicates the type of CRC that was used for the current data block:

  • 0: CRC24A
  • 1: CRC24B
Note: This signal is present only in LTE mode.
sel_CRC24A Input

Specifies the type of CRC that you need for the current data block:

  • 0: CRC24A
  • 1: CRC24B
Note: This signal is present only in LTE mode.
sink_blk_size Input Specifies the incoming block size. This signal needs to be held throughout the whole incoming block from SOP to EOP.
sink_data Input Input data.
sink_eop Input Indicates the end of an incoming packet.
sink_error Input Error signal indicating Avalon-ST protocol violations on input side.
sink_max_iter Input Specifies the maximum number of half-iterations. It must be even numbers for UMTS.
sink_ready Output Indicates when the IP core can accept data.
sink_sop Input Indicates the start of an incoming packet.
sink_valid Input Assert when data at sink_data is valid. When sink_valid is not asserted, processing stops until you reassert sink_valid.
source_blk_id Output Specifies the outgoing block ID.
source_blk_size Output Specifies the outgoing block size.
source_data_s Output Output data.
source_eop Output Indicates the end of an outgoing packet.
source_error Output

Error signal indicating Avalon-ST protocol violations on source side:

  • 00: No error
  • 01: Missing start of packet
  • 10: Missing end of packet
  • 11: Unexpected end of packet

Other types of errors may also be marked as 11.

source_iter Output Shows the number of half iterations after which the Turbo decoder stops processing the current data block. LTE only.
source_ready Input Asserted by the downstream module if it can accept data.
source_sop Output Indicates the start of an outgoing packet.
source_valid Output Asserted by the IP core when there is valid data to output.

Signals in Platform Designer (Standard) Systems

Platform Designer (Standard) systems instantiate all Turbo IP core signals as part of the Avalon-ST data bus.

Table 17.  Turbo Encoder Data Input
Bits Signal
N enc + 12:N enc sink_blk_size
N enc -1:0 sink_data
Table 18.  Turbo Encoder Data Output
Bits Signal
3 *N enc+12:3*N enc source_blk_size
3*N enc-1:0 source_data
Table 19.  Turbo Decoder Data InputIW is the number of bits for input precision.
Bits Signal
3*WLLR*NLLR+18 Sel_CRC24A (LTE only)
3*WLLR*NLLR+17:3*WLLR*NLLR+13 sink_max_iter
3*WLLR*NLLR+12:3*WLLR*NLLR sink_blk_size
3*WLLR*NLLR-1:0 sink_data
Table 20.  LTE Turbo Decoder Data Output
Bits Signal
Wout+19 CRC_Pass
Wout+18 CRC_type
Wout+17:Wout+13 source_iter
Wout+12:Wout source_blk_size
Wout-1:0 source_data
Table 21.  UMTS Turbo Decoder Data Output
Bits Signal
13:1 source_blk_size
0 source_data
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