## Turbo Intel® FPGA IP User Guide

ID 683734
Date 9/30/2021
Public

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## 4.2.3. Decoder Latency Calculation

The decoding delay D is the number of clock cycles the IP core consumes to decode an entire block of data. D depends on the block size, the number of iterations to perform, and the number of engines available in the decoder.

The following calculations assume no early termination for the worst case latency.

You can calculate the decoding delay D using one of the following equations:

• If K < 264: D = 26 + (2 × f(K,N) + 14) × 2 × I
• If K > 264, D = 26 + (f(K,N) + 46) × 2 × I

where:

• K is the block size
• I is the number of decoding iterations
• N dec is the number of engines specified in the decoder
For LTE,
• f(K,N dec) = K/N dec if K is divisible by N dec.
• f(K,N dec) = K/16 if K is not divisible by N dec, but it is divisible by 16.
• f(K,N dec) = K/8 in all other conditions.

For UMTS, f(K,N dec) = ceil(K/N dec)

For example:

• D = 26 + (6144/8 + 46) × 2 × 8 = 13,050, if K = 6144, N = 8, I = 8.
• D = 26 + (2 × 40/8 + 14) × 2 × 8 = 410, if K = 40, N = 8, I = 8.

You can calculate the decoding latency (the time the decoder takes to decode an entire block to the decoded data is ready for output) using the following equation:

L = D/f s

Where f is the system clock speed.