Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2021
Public

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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP Core User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Core Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.6. Simulating the Turbo IP with the C-Model x
2.6.1. Encoder Simulation 2.6.2. Decoder Simulation
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
4.3. x
4.3.1. Packet Format Errors
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP Core User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.3.1. Packet Format Errors

The Turbo IP interface complies with Avalon Streaming protocol. The Turbo IP is able to detect the following malformed Avalon Streaming sink packets that are mistakenly fed to the IP. If the IP detects an error , the current packet gets dropped and the output port source_error outputs the corresponding error code a few cycles later. Then, the IP continues to process the next available packet. Please note that the IP may not be able to detect complex error cases correctly. For instance, two or more of the following cases occur at the same time in a packet. Therefore, it is always recommended to protect the IP against malformed input packets when use in production.
  1. Error code "01" indicates missing sink_sop.
  2. Error code "10" indicates missing sink_eop.
  3. Error code "11" indicates unexpected sink_sop or sink_eop.
  4. Default "00" indicates no errors.
The IP input port sink_error accepts error code provided from the upstream block. However, a non-zero value from sink_error does not result in the current packet being dropped by the IP immediately. Instead the IP always detects errors itself. If IP founds an error, the current packet processed as normal and source_error is "00". If IP founds an error, the source_error signal is a combination of sink_error and the error detected by the IP itself, as follows:
  1. If error_found= 00, sink_error= any, then the source_error= 00.
  2. If error_found= 01, sink_error= 00 or 01, then the source_error= 01
  3. If error_found= 01, sink_error= 10 or 11, then the source_error= 11.
  4. If error_found= 10, sink_error= 00 or 10, then the source_error= 10.
  5. If error_found= 10, sink_error= 10 or 11, then the source_error= 11.
  6. If error_found= 11, sink_error= any, then the source_error= 11.
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