Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2021
Public

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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP Core User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Core Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.6. Simulating the Turbo IP with the C-Model x
2.6.1. Encoder Simulation 2.6.2. Decoder Simulation
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
4.3. x
4.3.1. Packet Format Errors
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP Core User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

2.6. Simulating the Turbo IP with the C-Model

Before simulating, generate the Turbo IP design example from the IP parameter editor.
Table 6.  Turbo C-Model versus Turbo IP Related Parameters
Turbo C-model Turbo IP Value
K Block size K, supports LTE standard -
CW sink_data (input codeword Ncb) -
llr_width Width of the input LLRs supports 5,6,7,8. 8
early_ter Early termination, always set to 1. 1
crc24b CRC_type,
  • 0: CRC24A
  • 1: CRC24B
 -
max_subiter sink_max_iter supports up to 31 (5 bits). -
nb_eng Number of Processors supports 2, 4, 8, 16, 32. 16
Iter_used source_iter Output
crc_pass CRC_pass Output
decoded_bits source_data_s Output
Level Two Title