Turbo Intel® FPGA IP User Guide

ID 683734
Date 9/30/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.6. Simulating the Turbo IP with the C-Model

Before simulating, generate the Turbo IP design example from the IP parameter editor.
Table 6.  Turbo C-Model versus Turbo IP Related Parameters
Turbo C-model Turbo IP Value
K Block size K, supports LTE standard -
CW sink_data (input codeword Ncb) -
llr_width Width of the input LLRs supports 5,6,7,8. 8
early_ter Early termination, always set to 1. 1
crc24b CRC_type,
  • 0: CRC24A
  • 1: CRC24B
-
max_subiter sink_max_iter supports up to 31 (5 bits). -
nb_eng Number of Processors supports 2, 4, 8, 16, 32. 16
Iter_used source_iter Output
crc_pass CRC_pass Output
decoded_bits source_data_s Output