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2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
1. About the Turbo Intel® FPGA IP
|Intel® Quartus® Prime Design Suite 20.4|
|IP Version 20.4.0|
The Turbo Intel® FPGA IP implements Turbo codes that is compliant with 3rd Generation Partnership Project (3GPP) LTE/LET-A and UMTS specification for integration in your wireless design. Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
Turbo codes are suitable for 3G and 4G mobile communications and satellite communications to help transmitting and receiving messages over noisy channels. You can also use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data corrupting noise.
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