Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 7/01/2021

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Document Table of Contents

6.1. Implementation of CvP Initialization Mode

CvP Initialization mode splits the bitstream into periphery and core images. The periphery image is stored in a local flash device on the PCB. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.

You must specify CvP Initialization mode in the Intel® Quartus® Prime Pro Edition software by selecting the CvP Settings Initialization and Update and you must also instantiate the PCI Express IP core. .

Note: The P-Tile Avalon Memory Mapped IP will not be available in the IP Catalog from Intel® Quartus® Prime Version 21.2 onwards. The replacement IP is the MCDMA-based PCI Express Avalon Memory Mapped IP.
Figure 8. Example Implementation Flow for CvP Initialization
The CvP Initialization demonstration (based on the Intel® Stratix® 10 FPGA Development Kit) walkthrough includes the following steps: