Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 7/01/2021
Public

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8. Document Revision History

Table 16.  Document Revision History for Intel® Stratix® 10 Configuration via Protocol Implementation User Guide
Document Version Intel® Quartus® Prime Version Changes
2021.07.01 21.2
Sections Updated:
2021.02.19 19.3
Sections updated:
  • CvP Modes
  • CvP System
  • Configuration Images
2020.09.22 19.3
  • Removed support for Avalon® Streaming (Avalon-ST) x8 configuration scheme.
  • Added a note in section CvP Systems to clarify the location of the PCIe* Hard IP block.
  • Added information about the supported tile in Table: CvP Support for Intel® Stratix® 10 Device Family.
2020.05.19 19.3 Corrected the file selection for AVST configuration mode in the following sections:
  • Converting the SOF File
  • Converting the SOF file of the Updated Revision
2020.01.10 19.3 Updated Figure: PCIe Timing Sequence in CvP Initialization Mode to include GPIO status.
2019.12.16 19.3
  • Added a link to the Intel Stratix 10 CvP Update Reference Design.
  • Updated following links:
    • CvP driver link
    • Intel Stratix 10 CvP Initialization Reference Design
  • Modified the steps in the following sections:
    • Creating a Reserved Core Partition
    • Setting up and Compile the Updated Revision
  • Added information about checking the .qsf file settings in Defining a Logic Lock Region section.
  • Modified step tp program the core.rbf file in section Programming the FPGA using the Base Revision Image.
2019.09.30 19.3
  • Added support for Avalon® Streaming x8 configuration scheme.
  • Replaced the Convert Programming File (CPF) tool related information with Programming File Generator (PFG) in the following sections:
    • Converting the SOF File
    • Converting the SOF File of the Updated Revision
2019.07.26 18.1
  • Corrected the byte offset for the CvP Programming Control Register.
  • Corrected register name in Figure 7: CvP Driver Flow.
2019.06.20 18.1 Clarified how to program the FPGA for CvP update mode.
2019.01.17 18.1
  • Modified the following in Setting up the Base Revision section:
    • Figure: Creating Design Partition from Project Navigator
    • Figure: Design Partitions Window
    • Figure: Creating Logic Lock Region from Project Navigator
  • Added Figure: Design Partitions Window in section Setting up and Compile the Updated Revision section.
2018.11.29 18.1 Modified the following diagrams:
  • Figure: Single Endpoint Topology
  • Figure: Multiple Endpoints Topology
2018.09.24 18.1
  • CvP update mode is now supported in the current version of the Intel® Quartus® Prime Pro Edition software.
  • Added new section Implementation of CvP Update Mode.
  • Modified diagrams:
    • Figure: Periphery and Core Image Storage Arrangement for CvP Core Image Update
    • Figure: Single Endpoint Topology
    • Figure: Multiple Endpoints Topology
  • Updated Figure: CvP Driver Flow in section CvP Driver Flow.
  • CVP_DATA2 register is no longer functional in Intel® Stratix® 10 devices.
  • Added new sections:
    • CvP Limitations and Restrictions
    • CvP Error Recovery
    • Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide Archives
2018.07.17 18.0
  • Added a note in CvP Modes section to clarify CvP update mode support in the current version of the Intel® Quartus® Prime Pro Edition software.
  • Modified Figure: PCIe Timing Sequence in CvP Initialization Mode diagram.
2018.06.18 18.0
  • Corrected the periphery image and core image definitions in Configuration Images section.
  • Added Figure: PCIe Timing Sequence in CvP Initialization Mode diagram and Table: Power-up Sequence Timing in CvP Initialization Mode information for CvP initialization.
  • Modified Figure: Single Endpoint Topology and Figure: Multiple Endpoint Topology in CvP Topologies chapter.
  • Added a note to clarify the Linux driver support provided by Intel® .
  • Updated the Figure: CvP Driver Flow.
  • Corrected the VSEC registers for CvP in VSEC Registers for CvP section.
  • Minor updates in Implementation of CvP Initialization Mode section.
Date Version Changes
December 2017 2017.12.18 Initial release.