Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 7/01/2021
Public

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Document Table of Contents

1.3. CvP Modes

The CvP configuration scheme supports the following modes:

  • CvP Initialization mode
  • CvP Update mode

CvP Initialization Mode

This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs through PCIe* link.

Benefits of using CvP Initialization mode include:

  • Satisfying the PCIe* wake-up time requirement
  • Saving cost by storing the core image in the host memory

CvP Update Mode

In the CvP update mode, you reconfigure the entire device except the CvP PCIe* core after the device enters the user mode through full chip configuration or CvP initialization. The subsequent core image updates use the PCIe* link (the periphery must not change during CvP update).

The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.

Choose this mode if you want to update the core image for any of the following reasons:

  • To change core algorithms logic blocks
  • To perform standard updates as part of a release process
  • To customize core processing for different components that are part of a complex system
Note: The CvP update mode is available after the FPGA enters user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.
Table 1.  CvP Support for Intel® Stratix® 10 Device Family
Supported Tile PCIe* Version Supported CvP Modes
H- and L-tile Gen 1 / Gen 2 / Gen 3 CvP Initialization, CvP Update
P-tile
Gen 1 / Gen 2 / Gen 3 / Gen 4
Note: You can only select Gen 3 and above in the PCIe* Hard IP, but the host can down-train the link to Gen 1 and Gen 2 if necessary.
Note: P-tile Gen 3x8 and Gen 4x8 cannot support CvP.