4.2. Designing CvP for a Closed System
While designing CvP for a closed system where you control both ends of the PCIe* link, estimate the periphery configuration time for CvP Initialization mode or full FPGA configuration time for CvP update mode. You must ensure that the estimated configuration time is within the time allowed by the PCIe* host. Your driver can poll the USERMODE bit of the CvP Status Register to determine if the FPGA enters the user mode.