Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 7/01/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

1.3.1. CvP Limitations and Restrictions

The Intel® Stratix® 10 CvP implementation has the following limitations and restrictions in the current version of the Intel® Quartus® Prime software:
  • Only MemWR transactions can be used to write fabric configuration data to the CvP data register. ConfigWR transactions are not supported.
  • When you poll the CVP_CREDIT bits from the CvP credit register, you must write the next 4KB of fabric configuration data to the CvP data register within 50 ms of receiving an additional credit. Failure to send the data results in configuration failure.
  • The CvP response time is variable and depends on different conditions. The typical delay time is 5 sec and it is safe to wait till 1 min. So the driver should poll status in credit register to decide on driver timeout.
  • In CvP initialization and update mode, when FPGA fabric is not programmed, the PCIe* features that uses FPGA fabric are not accessible.
  • To generate the update image in the CvP update mode, you must use the same version of the Intel® Quartus® Prime software that you use to generate the base image.