Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 7/01/2021

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6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express

Follow these steps to generate the synthesis HDL files with CvP enabled:
  1. Open the Intel® Quartus® Prime Pro Edition software.
  2. On the Tools menu, click Platform Designer . The Open System window appears.
  3. For System, click + and specify a File Name to create a new platform designer system. Click Create.
  4. On the System Contents tab, delete the clock_in and reset_in components that appear by default.
  5. In the IP Catalog locate and double-click Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express. The new window appears.
  6. On the IP Settings tab, specify the parameters and options for your design variation.
  7. On the Example Designs tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
  8. For Generated file format, only Verilog is available.
  9. For Target Development Kit, select the board of your choice.
  10. Click the Generate Example Design button. The Select Example Design Directory dialog box appears. Click OK. The software generates Intel® Quartus® Prime project files for PCI Express reference design. Click Close when generation completes. An example design pcie_s10_hip_ast_0_example_design is created in your project directory.
  11. Click Finish. Close your current project and open the generated PCI Express example design (pcie_example_design.qpf).
  12. Complete your CvP design by adding any desired top-level design and any other required modules. Pin assignments already being assigned properly based on the target development kit that user specified earlier.

Alternatively, you can download the complete Intel® Stratix® 10 CvP Initialization reference design from the link below.

Note: Reference design for CvP update is not available in the current version of the Intel® Quartus® Prime software.