1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 6. Document Revision History for the HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features
3.1. HDMI RX-TX Retransmit Design Block Diagram 3.2. Creating TX or RX Only Designs 3.3. Design Components 3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.5. Clocking Scheme 3.6. Interface Signals 3.7. Design RTL Parameters 3.8. Hardware Setup 3.9. Simulation Testbench 3.10. Upgrading Your Design
184.108.40.206. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.5. Security Considerations
When using the HDCP feature, be mindful of the following security considerations.
- When designing a repeater system, you must block the received video from entering the TX IP in the following conditions:
- If the received video is HDCP-encrypted (i.e. encryption status hdcp1_enabled or hdcp2_enabled from the RX IP is asserted) and the transmitted video is not HDCP-encrypted (i.e. encryption status hdcp1_enabled or hdcp2_enabled from the TX IP is not asserted).
- If the received video is HDCP TYPE 1 (i.e. streamid_type from the RX IP is asserted) and the transmitted video is HDCP 1.4 encrypted (i.e. encryption status hdcp1_enabled from the TX IP is asserted)
- You should maintain the confidentiality and integrity of your HDCP production keys, and any user encryption keys.
- Intel strongly recommends you to develop any Intel® Quartus® Prime projects and design source files that contain encryption keys in a secure compute environment to protect the keys.
- Intel strongly recommends you to use the design security features in FPGAs to protect the design, including any embedded encryption keys, from unauthorized copying, reverse engineering, and tampering.