1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel®...

HDMI Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683701

Date 9/07/2022

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Document Table of Contents

Document Table of Contents x

1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 6. Document Revision History for the HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide

1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices x

1.1. Directory Structure 1.2. Generating the Design 1.3. Hardware and Software Requirements 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters

2. HDMI 2.1 Design Example (Support FRL = 1) x

2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features

2.5. Design Components x

2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks

2.15. Debugging Features x

2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement

3. HDMI 2.0 Design Example x

3.1. HDMI RX-TX Retransmit Design Block Diagram 3.2. Creating TX or RX Only Designs 3.3. Design Components 3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.5. Clocking Scheme 3.6. Interface Signals 3.7. Design RTL Parameters 3.8. Hardware Setup 3.9. Simulation Testbench 3.10. Upgrading Your Design

4. HDCP Over HDMI 2.0/2.1 Design Example x

4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines

4.1. High-bandwidth Digital Content Protection (HDCP) x

4.1.1. HDCP Over HDMI Design Example Architecture

4.3. Design Walkthrough x

4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results

4.3.3. Include HDCP Production Keys x

4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)

4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x

4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file

4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x

4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer

4.3.5. View the Results x

4.3.5.1. Push Buttons and LED Functions

4.6. Debug Guidelines x

4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)

1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices

1.1. Directory Structure

1.2. Generating the Design

1.3. Hardware and Software Requirements

1.4. Simulating the Design

1.5. Compiling and Testing the Design

1.6. Design Limitation

1.7. HDMI Intel® FPGA IP Design Example Parameters

2. HDMI 2.1 Design Example (Support FRL = 1)

2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram

2.2. Creating RX-Only or TX-Only Designs

2.3. Hardware and Software Requirements

2.4. Directory Structure

2.5. Design Components

2.5.1. HDMI TX Components

2.5.2. HDMI RX Components

2.5.3. Top-Level Common Blocks

2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering

2.7. Design Software Flow

2.8. Running the Design in Different FRL Rates

2.9. Clocking Scheme

2.10. Interface Signals

2.11. Design RTL Parameters

2.12. Hardware Setup

2.13. Simulation Testbench

2.14. Design Limitations

2.15. Debugging Features

2.15.1. Software Debugging Message

2.15.2. SCDC Information from the Sink Connected to TX

2.15.3. Clock Frequency Measurement

3. HDMI 2.0 Design Example

3.1. HDMI RX-TX Retransmit Design Block Diagram

3.2. Creating TX or RX Only Designs

3.3. Design Components

3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering

3.5. Clocking Scheme

3.6. Interface Signals

3.7. Design RTL Parameters

3.8. Hardware Setup

3.9. Simulation Testbench

3.10. Upgrading Your Design

4. HDCP Over HDMI 2.0/2.1 Design Example

4.1. High-bandwidth Digital Content Protection (HDCP)

4.1.1. HDCP Over HDMI Design Example Architecture

4.2. Nios II Processor Software Flow

4.3. Design Walkthrough

4.3.1. Set Up the Hardware

4.3.2. Generate the Design

4.3.3. Include HDCP Production Keys

4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0)

4.3.3.1.1. HDCP Key Mapping from DCP Key Files

4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files

4.3.3.1.3. hdcp2x_rx_kmem.v file

4.3.3.1.4. hdcp2x_tx_kmem.v file

4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)

4.3.3.2.1. Intel KEYENC

4.3.3.2.2. Key Programmer

4.3.4. Compile the Design

4.3.5. View the Results

4.3.5.1. Push Buttons and LED Functions

4.4. Protection of Encryption Key Embedded in FPGA Design

4.5. Security Considerations

4.6. Debug Guidelines

4.6.1. HDCP Status Signals

4.6.2. Modifying HDCP Software Parameters

4.6.3. Frequently Asked Questions (FAQ)

5. HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide Archives

6. Document Revision History for the HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide

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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices

Updated for:
Intel® Quartus® Prime Design Suite 22.2
IP Version 19.7.0

The HDMI Intel® FPGA IP design example for Intel® Stratix® 10 devices features a simulating testbench and a hardware design that supports compilation and hardware testing.

The HDMI Intel® FPGA IP offers the following design examples:

HDMI 2.1 RX-TX retransmit design with fixed rate link (FRL) mode enabled
HDMI 2.0 RX-TX retransmit design
HDCP over HDMI 2.0 design
Note: The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Figure 1. Development Steps