HDMI Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683701
Date 9/07/2022
Document Table of Contents

1.6. Design Limitation

You need to consider some limitations when instantiating the HDMI Intel® FPGA IP design examples.

  • You may encounter longer lock time using the HDMI RX for HDMI 2.0 resolution. This limitation will be resolved in a future release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message