Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683699
Date 3/08/2022
Public

3.1.4. LAB Control Signals

Each LAB supports a single clock to drive the ALM registers in the LAB. The LAB supports two unique clock enable signals, as well as additional clear signals, for the ALM registers.

In addition, each LAB control block drives clock signals for the Hyper-Registers. There is a single clock for the Hyper-Registers on the local interconnect, and additional clocks for the Hyper-Registers located at the ALM inputs.

The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. A low skew clock network distributes global signals to the row clocks [5..0]. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for routing efficiency. The Intel® Quartus® Prime Compiler automatically routes critical design paths on faster interconnects to improve design performance and optimizes the device resources.

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