Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

ID 683699
Date 3/27/2022
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4. Document Revision History for the Intel® Stratix® 10 LAB and ALM User Guide

Document Version Changes
2023.03.27 Corrected error where Intel Agilex® was mentioned instead of Intel® Stratix® 10.
2022.03.08 Updated Figure: Intel® Stratix® 10 ALM Connection Details.
2020.04.24 Updated the Clear Logic Control section to remove the DEV_CLRn pin.
2018.09.21
  • Updated the Intel® Stratix® 10 ALM High-Level Block Diagram figure.
  • Updated the Intel® Stratix® 10 ALM Connection Details figure.
  • Updated the ALM in Normal Mode figure.
  • Updated the 3-Input LUT Mode Function in Normal Mode figure.
  • Updated the Supported 8-Input Functions in the Extended LUT Mode figure.
  • Updated the Intel® Stratix® 10 ALM in Arithmetic Mode figure.
  • Updated the Normal Mode section.
  • Updated the Extended LUT Mode section.
Date Version Changes
November 2017 2017.11.06
  • Added the 6-Input LUT Mode Function in Normal Mode figure.
  • Update the Intel® Stratix® 10 LAB and ALM Overview section.
  • Updated the Carry Chain section.
  • Updated the Intel® Stratix® 10 ALM High-Level Block Diagram figure.
  • Updated the hyperflex registers in the Intel® Stratix® 10 ALM Connection Details figure.
October 2016 2016.10.31

Initial release.