Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

ID 683699
Date 3/08/2022
Public Carry Chain

The carry chain provides a fast carry function between the dedicated adders in the arithmetic mode.

The 2-bit carry select feature in Intel® Stratix® 10 devices splits the propagation delay of carry chains with the ALM. Carry chains can begin in either the first ALM or the sixth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.

To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use the bottom half of the LAB before connecting to the next LAB. You can use the available top half of the ALMs in the LAB to implement narrower fan-in functions in the normal mode. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. The behavior is the same for both the LAB and the MLAB columns.

The Intel® Quartus® Prime Compiler creates carry chains longer than 20 ALUTs (10 ALMs in arithmetic) by linking LABs together. For an enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks.

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