Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683699
Date 3/08/2022
Public

3.2.1. ALM Resources

Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs), a two-bits full adder, and four registers.

With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four input LUT architectures. One ALM can also implement a subset of eight input functions.

One ALM contains four programmable registers. Each register has the following ports:

  • Data in
  • Data out
  • Clock
  • Clock enable
  • Synchronous clear
  • Asynchronous clear

Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock enable signal, clock, and asynchronous or synchronous clear control signals of an ALM register. The clock enable signal has priority over synchronous reset signal.

For combinational functions, the registers are bypassed and the output of the look-up table (LUT) and adders drives directly to the outputs of an ALM.

Figure 6.  Intel® Stratix® 10 ALM High-Level Block Diagram

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