Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

Download
ID 683699
Date 3/08/2022
Public

3.1.4.1. Clear Logic Control

LAB-wide signals control the logic for the ALM register's clear signal. The ALM register directly supports both a synchronous and an asynchronous clear. Each LAB supports one synchronous clear signal and two asynchronous clear signals.

Figure 5.  Intel® Stratix® 10 LAB-Wide Control Signals

Did you find the information on this page useful?

Characters remaining:

Feedback Message