Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683699
Date 3/08/2022
Public

2. Intel® Hyperflex™ Register

The Intel® Stratix® 10 device family introduces the Intel® Hyperflex™ core architecture.

The Intel® Stratix® 10 LAB contains Intel® Hyperflex™ registers and other features designed to facilitate retiming. Intel® Hyperflex™ registers are available in ALMs and carry chain. As shown in the Intel® Stratix® 10 ALM Connection Details figure, the Intel® Hyperflex™ registers are located on the synchronous clear and clock enable inputs to increase or reduce effective path delay. All the Intel® Hyperflex™ registers can be enabled and are controlled by the Intel® Quartus® Prime software during retiming.

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