Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

Download PDF
ID 683699
Date 3/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel® Stratix® 10 LAB and ALM Architecture and Features 4. Document Revision History for the Intel® Stratix® 10 LAB and ALM User Guide
3. Intel® Stratix® 10 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel® Stratix® 10 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel® Stratix® 10 LAB and ALM Architecture and Features
4. Document Revision History for the Intel® Stratix® 10 LAB and ALM User Guide

2. Intel® Hyperflex™ Register

The Intel® Stratix® 10 device family introduces the Intel® Hyperflex™ core architecture.

The Intel® Stratix® 10 LAB contains Intel® Hyperflex™ registers and other features designed to facilitate retiming. Intel® Hyperflex™ registers are available in ALMs and carry chain. As shown in the Intel® Stratix® 10 ALM Connection Details figure, the Intel® Hyperflex™ registers are located on the synchronous clear and clock enable inputs to increase or reduce effective path delay. All the Intel® Hyperflex™ registers can be enabled and are controlled by the Intel® Quartus® Prime software during retiming.

Level Two Title