eCPRI Intel® FPGA IP User Guide

ID 683685
Date 11/11/2021

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Document Table of Contents

4.2.1. Transmit TX Path

There are two sets of Avalon-ST source and sink interface signals available to the incoming packets on the transmit TX path. Avalon-ST source/sink interface connects to the eCPRI IP and external source/sink interface connects to external user logic. The incoming eCPRI packets passes through Ethernet header insertion block to insert Ethernet header, optionally with different VLAN tags, IPv4, and UDP headers configured during configuration time.

You can send different types of packets through the external source/sink interface signal (For example, C&M and synchronization packets) which arbitrates with eCPRI packets and the IP sends packets with the higher priority to Ethernet MAC for transmission. The incoming external user packets are expected to arrive with Ethernet MAC header inserted on the packets.

The priority of the packets send to Ethernet MAC is listed as below, with highest priority order from top to bottom:
  • PTP synchronization packet
  • eCPRI packet
  • C&M packets and remaining type of packets

The C&M and PTP synchronization packets are send/receive through external source/sink interface signal. The C&M and PTP synchronization packets are generally low bandwidth traffic. When there is collision between external PTP synchronization packets and eCPRI packets, backpressure to the eCPRI IP occurs to stop eCPRI packets from transmitting. The eCPRI IP implements a counter to track the number of eCPRI packets and PTP packets granted and raise the priority of the C&M packet when the counter reaches a programmable threshold to allow the C&M packet transmission to Ethernet MAC and avoid starvation.

Ensure the bandwidth of external source/sink interface signal won't starve the overall bandwidth and cause interruption on eCPRI traffics. The grant ratio between C&M packets versus eCPRI/PTP packets is 10:1. The bandwidth allocated to C&M packets is 2.5G or 1G. The maximum C&M/PTP FIFO depth is 256 or 2048 bytes for eCPRI IP. The C&M/PTP FIFO should not be kept full beyond 2062.5 * (mac_clk_tx) clock period, to allow for enough read margin prior to the arrival of the new packets.

When you set the Ethernet frame size to 9000 bytes, data from Avalon-ST sink interface directly pass through and does not required buffering. You must assert avst_sink_valid continuously between the assertions of avst_sink_sop and avst_sink_eop. The only exception is when avst_sink_ready signal deasserts, and you are required to deassert avst_sink_valid for three cycles of READY_LATENCY.