eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 11/11/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon-MM Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
6. Registers x
6.1. eCPRI Version Register 6.2. eCPRI Scratch Register 6.3. eCPRI Common Control Register 6.4. eCPRI Message 5 Control Register 6.5. eCPRI TX Error Message Register 6.6. eCPRI RX Error Message Register 6.7. eCPRI Error Mask Message Register 6.8. eCPRI Error Log Message Register 6.9. eCPRI Error Message 5 Compensation Value 0 Register 6.10. eCPRI Error Message 5 Compensation Value 1 Register 6.11. eCPRI Transport Delay 0 Register 6.12. eCPRI Transport Delay 1 Register 6.13. eCPRI Transport Delay 2 Register 6.14. Ethernet Frame Scratch Register 6.15. Source MAC Address <i> Register, where i= 0, 1 6.16. Destination MAC n Address <i> Register, where n= 0, 1, 2, 3, 4, 5, 6, 7 and i= 0, 1 6.17. VLAN Tag Register <i>, where i= 0, 1, 2, 3, 4, 5, 6, 7 6.18. Ethertype Register 6.19. IPv4 Dw0 Register 6.20. IPv4 Dw1 Register 6.21. IPv4 Dw2 Register 6.22. IPv4 Source Address Register 6.23. IPv4 Destination Address Register 6.24. UDP Dw0 Register 6.25. UDP Port Register 6.26. MAC Packet Type Enable Register 6.27. RX Error Register
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

5.14.1. IWF Source Interface

Table 40.  Signals of the IWF Source InterfaceAll signals are synchronous to clk_tx.
Signal Name Width (Bits) I/O Direction Description
iwf_avst_source_valid 1 Output Avalon source valid from eCPRI IP to client logic.
iwf_avst_source_data DATA_WIDTH 10 Output Avalon source write data from eCPRI IP to client logic.
iwf_avst_source_sop 1 Output Avalon source start of packet from eCPRI IP to client logic. Indicates the beginning of packet.
iwf_avst_source_eop 1 Output Avalon source end of packet from eCPRI IP to client logic. Indicates the end of packet.
iwf_avst_source_empty LOG2(DATA_WIDTH10/8) Output Avalon source empty from eCPRI IP to client logic. Indicates the number of symbols that are empty, that is, do not represent valid data.
iwf_avst_source_error 1 Output Avalon source error from eCPRI IP to client logic. A bit mask to mark errors affecting the data being transferred in the current cycle.
iwf_gmii_rxdv[N] 1 Input Ethernet receive data valid. Indicates the presence of valid data or initial start-of-packet control character on iwf_gmii_rxd.

This signal is from IWF to user logic.

iwf_gmii_rxer[N] 1 Input Ethernet receive error. Indicates an error on iwf_gmii_rxd. When this signal is asserted, the value on iwf_gmii_rxd is 0x0E.

This signal is from user logic to IWF.

iwf_gmii_rxd[N] 8 Input Ethernet receive data. Data bus for data from the IWF to the external Ethernet block.

This signal is from user logic to IWF.
iwf_gmii_rxfifo_status[N] 4 Input Ethernet RX PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3]: Empty
  • Bit [2]: Almost empty
  • Bit [1]: Full
  • Bit [0]: Almost full

This signal is from user logic to IWF.
iwf_gmii_txen[N] 1 Output Valid signal for GMII interface that indicate data is valid. This signal required to be asserted two clock cycles earlier for the character S to be inserted into the data stream as the start of packet before takes in the real GMII data. The deassertion of this signal trigger the assertion of /T/R as the representation of end of packet.

This signal is from user logic to IWF.
iwf_gmii_txer[N] 1 Output Ethernet transmit coding error.

This signal is from user logic to IWF.

iwf_gmii_txd[N] 8 Output Ethernet transmit data.

This signal is from user logic to IWF.

iwf_gmii_txfifo_status[N] 4 Input Ethernet TX PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3]: Empty
  • Bit [2]: Almost empty
  • Bit [1]: Full
  • Bit [0]: Almost full

This signal is from user logic to IWF.
Sideband
iwf_source_pkt_size 16 Output Indicates IWF to eCPRI IP packet size in bytes.
CPRI Line Bit Rate (Gbps) Packet Size (Byte)
Ctel_AxC and RTVS IQ Data
0.6144 1 15
1.2288 2 30
2.4756 4 60
3.0720 5 75
4.9152 8 120
6.1440 10 120
8.11008 16 240
9.8304 16 240
10.1376 16
Note: For RTVS, the value is 4.
300
12.16512 16
Note: For RTVS, the value is 8.
360
24.33024 16
Note: For RTVS, the value is 32.
720
iwf_source_pkt_checksum 16 Output Checksum for data packet from IWF to eCPRI IP.

This signal is used for UPD checksum.

iwf_source_concatenation 1 Output Concatenation indication on the eCPRI message:
  • 0: Indicates that the eCPRI message is the last one inside the eCPRI PDU.
  • 1: Indicates that another eCPRI message follows this one within the eCPRI PDU.
Valid on SOP assertion and stable until EOP assertion.
Note: IWF do not support concatenation.
iwf_source_pc_id 16 Output Physical channel ID of the eCPRI message. Lower byte maps to CPRI channel. Only channel 0 is supported in the current release.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_seq_id 16 Output Sequence ID of the eCPRI message.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_rtc_id 16 Output Real Time Control ID of the eCPRI message.

Valid on SOP assertion and stable until EOP assertion.

Valid values are:
  • ID [7:0]: CPRI channel
  • ID [11:8]: 'h0- Ctrl_AxC, 'h1- Vendor Specific, 'h2- Real-time Vendor Specific
iwf_source_msg_type 8 Output Indicate message type of the eCPRI message. IWF type 0 supports only message type 0, 2, 6 and 7.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_reset_id 16 Output Indicate reset ID of the eCPRI message type 6. Lower byte maps to CPRI channel. Only channel 0 is supported in the current release.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_reset_op 8 Output Indicate reset operation type of the eCPRI message type 6:
  • 8’b00000000- Remote Reset Request
  • 8’b00000001- Remote Reset Response
  • Others- Reserved

Valid on SOP assertion and stable until EOP assertion.

iwf_source_event_id 8 Output Indicates event ID of the eCPRI message type 7. Lower byte maps to CPRI channel. Only channel 0 is supported in the current release.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_event_type 8 Output Indicates event type of the eCPRI message type 7.

Valid on SOP assertion and stable until EOP assertion.

iwf_source_notif 8 Output Indicates number of faults withing eCPRI message type 7.

Valid on SOP assertion and stable until EOP assertion.

10 This is set to 64. This parameter is hidden from user and you can't change it.
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