Visible to Intel only — GUID: qwb1601570882110
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4.3.8.1. eCPRI Message Type 0- IQ Data Transfer
4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer
4.3.8.3. eCPRI Message Type 2- Real Time Control Data
4.3.8.4. eCPRI Message Type 3- Generic Data Transfer
4.3.8.5. eCPRI Message Type 4- Remote Memory Access
4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement
4.3.8.7. eCPRI Message Type 6- Remote Reset
4.3.8.8. eCPRI Message Type 7- Event Indication
4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5.1. Clock Signals
5.2. Power, Reset, and Firewalls Signals
5.3. TX Time of Day Interface
5.4. RX Time of Day Interface
5.5. Interrupt
5.6. Configuration Avalon-MM Interface
5.7. Ethernet MAC Source Interface
5.8. Ethernet MAC Sink Interface
5.9. External ST Source Interface
5.10. External ST Sink Interface
5.11. eCPRI IP Source Interface
5.12. eCPRI IP Sink Interface
5.13. Miscellaneous Interface Signals
5.14. IWF Type 0 eCPRI Interface
5.15. IWF Type 0 CPRI MAC Interface
5.15.1. CPRI 32-bit IQ Data TX Interface
5.15.2. CPRI 64-bit IQ Data TX Interface
5.15.3. CPRI 32-bit Ctrl_AxC TX Interface
5.15.4. CPRI 64-bit Ctrl_AxC TX Interface
5.15.5. CPRI 32-bit Vendor Specific TX Interface
5.15.6. CPRI 64-bit Vendor Specific TX Interface
5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface
5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface
5.15.9. CPRI Gigabit Media Independent Interface (GMII)
5.15.10. CPRI IP L1 Control and Status Interface
6.1. eCPRI Version Register
6.2. eCPRI Scratch Register
6.3. eCPRI Common Control Register
6.4. eCPRI Message 5 Control Register
6.5. eCPRI TX Error Message Register
6.6. eCPRI RX Error Message Register
6.7. eCPRI Error Mask Message Register
6.8. eCPRI Error Log Message Register
6.9. eCPRI Error Message 5 Compensation Value 0 Register
6.10. eCPRI Error Message 5 Compensation Value 1 Register
6.11. eCPRI Transport Delay 0 Register
6.12. eCPRI Transport Delay 1 Register
6.13. eCPRI Transport Delay 2 Register
6.14. Ethernet Frame Scratch Register
6.15. Source MAC Address <i> Register, where i= 0, 1
6.16. Destination MAC n Address <i> Register, where n= 0, 1, 2, 3, 4, 5, 6, 7 and i= 0, 1
6.17. VLAN Tag Register <i>, where i= 0, 1, 2, 3, 4, 5, 6, 7
6.18. Ethertype Register
6.19. IPv4 Dw0 Register
6.20. IPv4 Dw1 Register
6.21. IPv4 Dw2 Register
6.22. IPv4 Source Address Register
6.23. IPv4 Destination Address Register
6.24. UDP Dw0 Register
6.25. UDP Port Register
6.26. MAC Packet Type Enable Register
6.27. RX Error Register
Visible to Intel only — GUID: qwb1601570882110
Ixiasoft
5.15.4. CPRI 64-bit Ctrl_AxC TX Interface
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
TX Interface | |||
ctr64_axc_tx_ready[N] | 8 | Input | Each asserted bit indicates the CPRI mapper is ready to read Ctrl_Axc data from the corresponding byte of ctrl_axc_tx_data on the next clock cycle. |
ctrl64_axc_tx_valid[N] | 8 | Output | Write valid for ctrl_axc_tx_data. Assert bit [n] to indicate that the corresponding byte on the current ctrl_axc_tx_data bus is valid Ctrl_AxC data. |
ctrl64_axc_tx_data[N] | 64 | Output | Ctrl_AxC data to be written to the CPRI frame. The CPRI mapper writes the individual bytes of the current value on the ctrl_axc_tx_data bus to the CPRI frame based on the ctrl_axc_tx_ready signal from the previous cycle, and the ctrl_axc_tx_valid signal in the current cycle. |
RX Interface | |||
ctrl64_axc_rx_valid[N] | 4 | Input | Assertion of the bit indicates the corresponding byte on the current ctrl64_axc_rx_data bus is valid Ctrl_AxC data. |
ctrl64_axc_rx_data[N] | 64 | Input | IQ data received from the CPRI frame. The ctrl64_axc_rx_valid signal indicates valid Ctrl AxC data bytes. |