eCPRI Intel® FPGA IP User Guide

ID 683685
Date 11/11/2021

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Document Table of Contents

5.15.1. CPRI 32-bit IQ Data TX Interface

Table 42.  Signals of CPRI 32-bit IQ Data Interface
Signal Name Width (Bits) I/O Direction Description
TX Interface
iq32_tx_ready[N] 4 Input Each asserted bit indicates the IP core is ready to write IQ data into iq_tx_datain the next clock cycle. Each bit represents readiness of each byte.
iq32_tx_valid[N] 4 Output Write valid for iq_tx_data.
iq32_tx_data[N] 64 Output Respective IQ data word or bytes to be written based on iq_tx_ready signal.
RX Interface
iq32_rx_valid[N] 4 Input Assertion of the bit indicates the corresponding byte on the current iq_rx_data bus is valid IQ data.
iq32_rx_data[N] 64 Input IQ data received from the CPRI frame. The iq_rx_valid signal indicates valid I/Q data bytes.