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Ixiasoft
Visible to Intel only — GUID: ann1601570906948
Ixiasoft
5.15.5. CPRI 32-bit Vendor Specific TX Interface
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
TX Interface | |||
vs32_tx_ready[N] | 4 | Input | Indicates that CPRI mapper is ready to read a real-time vendor specific byte from vs_tx_data on the next clock cycle. |
vs32_tx_valid[N] | 4 | Output | Write valid for vs_tx_data. Assert this signal to indicate vs_tx_data holds a valid value in the current clock cycle |
vs32_tx_data[N] | 64 | Output | Real-time vendor specific word to be written to the CPRI frame. The CPRI mapper writes the current value of the vs_tx_data bus to the CPRI frame based on the vs_tx_ready signal from the previous cycle, and the vs_tx_valid signal in the current cycle. |
RX Interface | |||
vs_rx_valid[N] | 4 | Input | Each asserted bit indicates the corresponding byte on the current vs_rx_data bus is a valid vendor specific byte. |
vs_rx_data[N] | 64 | Input | Indicates vendor specific word received from the CPRI frame. The vs_rx_valid signal indicates which bytes are valid vendor specific bytes. |