Intel Agilex® 7 Configuration User Guide

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ID 683673
Date 4/28/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Configuration User Guide 2. Intel Agilex® 7 Configuration Details 3. Intel Agilex® 7 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel Agilex® 7 Configuration Features 7. Intel Agilex® 7 Debugging Guide 8. Intel Agilex® 7 Configuration User Guide Archives 9. Document Revision History for the Intel Agilex® 7 Configuration User Guide
1. Intel Agilex® 7 Configuration User Guide x
1.1. Intel Agilex® 7 Configuration Overview 1.2. Intel Agilex® 7 Configuration Architecture
1.1. Intel Agilex® 7 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex® 7 Devices
1.2. Intel Agilex® 7 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Updating the SDM Firmware 1.2.1.2. Specifying Boot Order for Intel Agilex® 7 SoC Devices
2. Intel Agilex® 7 Configuration Details x
2.1. Intel Agilex® 7 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel Agilex® 7 Configuration Pins 2.6. Configuration Clocks 2.7. Intel Agilex® 7 Configuration Time Estimation 2.8. Generating Compressed .sof File
2.5. Intel Agilex® 7 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. I/O Standards and Features for Configuration Pins 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.5.3.3. I/O Standards and Features for Configuration Pins x
2.5.3.3.1. IBIS Model
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Intel Agilex® 7 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core x
3.1.7.1. Functional Description 3.1.7.2. Designing with the PFL II IP Core for Avalon-ST Single Device Configuration 3.1.7.3. Generating the PFL II IP Core 3.1.7.4. Constraining the PFL II IP Core 3.1.7.5. Using the PFL II IP Core 3.1.7.6. Supported Flash Memory Devices
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the PFL II IP Core for Avalon-ST Single Device Configuration x
3.1.7.2.1. PFL II Parameters 3.1.7.2.2. PFL II Signals
3.1.7.3. Generating the PFL II IP Core x
3.1.7.3.1. Controlling Avalon-ST Configuration with PFL II IP Core 3.1.7.3.2. Mapping PFL II IP Core and Flash Address 3.1.7.3.3. Creating a Single PFL II IP for Programming and Configuration 3.1.7.3.4. Creating Separate PFL II Functions
3.1.7.4. Constraining the PFL II IP Core x
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins 3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the PFL II IP Core x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
3.2.5. Skew Tolerance Guidelines x
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Intel® Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Embedded Memory Block Initial Conditions 4.5.3. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example 5.7. Debugging Guidelines for RSU Configuration
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Intel Agilex® 7 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Intel Agilex® 7 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Intel Agilex® 7 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior
1. Intel Agilex® 7 Configuration User Guide
2. Intel Agilex® 7 Configuration Details
3. Intel Agilex® 7 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel Agilex® 7 Configuration Features
7. Intel Agilex® 7 Debugging Guide
8. Intel Agilex® 7 Configuration User Guide Archives
9. Document Revision History for the Intel Agilex® 7 Configuration User Guide

3.1.7.2.1. PFL II Parameters

Table 25.  PFL II General Parameters
Options Value Description
What operating mode will be used?
  • Flash Programming
  • FPGA Configuration
  • Flash Programming and FPGA Configuration
Specifies the operating mode of flash programming and FPGA configuration control in one IP core or separate these functions into individual blocks and functionality.
What is the targeted flash?
  • CFI Parallel Flash
  • Quad SPI Flash

Specifies the flash memory device connected to the PFL II IP core.
Set flash bus pins to tri-state when not in use
  • On
  • Off
Allows the PFL II IP core to tri-state all pins interfacing with the flash memory device when the PFL II IP core does not require access to the flash memory.
Table 26.  PFL II Flash Interface Setting Parameters for CFI Parallel Flash These settings are available only when CFI Parallel Flash is selected as the targeted flash.
Options Value Description
How many flash devices will be used?
  • 1–16
Specifies the number of flash memory devices connected to the PFL II IP core.
What's the largest flash device that will be used?
  • 8 Mbit–4 Gbit

Specifies the density of the flash memory device to be programmed or used for FPGA configuration. If you have more than one flash memory device connected to the PFL II IP core, specify the largest flash memory device density.

For dual CFI flash, select the density that is equivalent to the sum of the density of two flash memories. For example, if you use two 512-Mb CFI flashes, you must select CFI 1 Gbit.

What is the flash interface data width
  • 8
  • 16
  • 32

Specifies the flash data width in bits. The flash data width depends on the flash memory device you use. For multiple flash memory device support, the data width must be the same for all connected flash memory devices.

Select the flash data width that is equivalent to the sum of the data width of two flash memories. For example, if you are targeting dual solution, you must select 32 bits because each CFI flash data width is 16 bits.

Allow user to control FLASH_NRESET pin
  • On
  • Off

Creates a FLASH_NRESET pin in the PFL II IP core to connect to the reset pin of the flash memory device. A low signal resets the flash memory device. In burst mode, this pin is available by default.

Table 27.  PFL II Flash Interface Setting Parameters for Quad SPI Flash These settings are available only when Quad SPI Flash is selected as the targeted flash.
Options Value Description
How many flash devices will be used?
  • 1
  • 2
  • 4
  • 8
Specifies the number of flash memory devices connected to the PFL II IP core.
What's the Quad SPI flash device manufacturer?
  • Micron
  • Macronix

Specifies the Quad SPI flash device manufacturer.

What is the Quad SPI flash device density?
  • QSPI 8 Mbit
  • QSPI 16 Mbit
  • QSPI 32 Mbit
  • QSPI 64 Mbit
  • QSPI 128 Mbit
  • QSPI 256 Mbit
  • QSPI 512 Mbit
  • QSPI 1 Gbit
  • QSPI 2 Gbit
Specifies the density of the flash memory device to be programmed or used for FPGA configuration. For Macronix flash memory devices, only devices with 2 Gbit of flash memory are supported for PFL II IP core.
Table 28.  PFL II Flash Programming Parameters
Options Value Description
Flash programming IP optimization target
  • Area
  • Speed
Specifies the flash programming IP optimization. If you optimize the PFL II IP core for Speed, the flash programming time is shorter, but the IP core uses more LEs. If you optimize the PFL II IP core for Area, the IP core uses fewer LEs, but the flash programming time is longer.
Flash programming IP FIFO size
  • 16
  • 32
Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL II IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming. With a larger FIFO size, programming time is shorter.
Add Block-CRC verification acceleration support
  • On
  • Off
Adds a block to accelerate verification.
Table 29.  PFL II FPGA Configuration Parameters
Options Value Description
What is the external clock frequency? Provide the frequency of your external clock. Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The clock frequency must not exceed two times the maximum clock (AVST_CLK) frequency the FPGA can use for configuration. The PFL II IP core can divide the frequency of the input clock maximum by two.
What is the flash access time? Provide the access time from the flash data sheet.

Specifies the flash access time. This information is available from the flash datasheet. Intel recommends specifying a flash access time that is equal to or greater than the required time.

For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time. This option is disabled for quad SPI flash.

What is the byte address of the option bits, in hex? Provide the byte address of the option bits.

Specifies the option bits start address in flash memory. The start address must reside on an 8 KB boundary. This address must be the same as the bit sector address you specified when converting the .sof to a .pof.

For more information refer to Storing Option Bits.

Which FPGA configuration scheme will be used?
  • Avalon® -ST x8
  • Avalon® -ST x16
  • Avalon® -ST x32
Specifies the width of the Avalon® -ST interface.
What should occur on configuration failure?
  • Halt
  • Retry same page
  • Retry from fixed address
Configuration behavior after configuration failure.
  • If you select Halt, the FPGA configuration stops completely after failure.
  • If you select Retry same page, after failure, the PFL II IP core reconfigures the FPGA with data from the page that failed.
  • If you select Retry from fixed address, the PFL II IP core reconfigures the FPGA a fixed address.
What is the byte address to retry from failure — If you select Retry from fixed address for configuration failure option, this option specifies the flash address the PFL II IP core to reads from.
Include input to force reconfiguration
  • On
  • Off
Includes the optional pfl_nreconfigure reconfiguration input pin to enable reconfiguration of the FPGA.
Enable watchdog timer on Remote System Update support
  • On
  • Off
Enables a watchdog timer for remote system update support. Turning on this option enables the pfl_reset_watchdog input pin and pfl_watchdog_error output pin. This option also specifies the period before the watchdog timer times out. The watchdog timer runs at the pfl_clk frequency.
Time period before the watchdog timer times out — Specifies the time out period for the watchdog timer. The default time out period is 100 ms.
Use advance read mode?
  • Normal mode
  • Intel Burst mode
  • 16 byte page mode (GL-S only)
  • 32 byte page mode (MT28EW)
This option improves the overall flash access time for the read process during the FPGA configuration.
  • Normal mode—applicable for all flash memory
  • Intel Burst mode—Applicable for devices that support bursting. Reduces sequential read access time
  • 16 byte page mode (GL-S only)—applicable for Infineon GL-S flash memory only
  • 32 byte page mode (MT28EW)—applicable for MT28EW only
For more information about the read-access modes of the flash memory device, refer to the respective flash memory data sheet.
Latency count
  • 3
  • 4
  • 5
Specifies the latency count for Intel Burst mode.
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