Intel Agilex® 7 Configuration User Guide

ID 683673
Date 4/28/2023
Public
Document Table of Contents

6.3. Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can define multiple personas for a region in your design, without impacting operation in areas outside this region. This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.

Did you find the information on this page useful?

Characters remaining:

Feedback Message